1. Field of the Invention
The present invention relates to a frequency synthesizer device and a mobile radio device using the same and, more particularly, a frequency synthesizer device in which a power supply voltage of a frequency-division ratio control circuit is lowered and a mobile radio device using the same.
2. Description of the Related Art
In the case of the mobile radio device, for example, the frequency synthesizer device is used to produce the carrier wave with any frequency from the reference signal. Thus, the high-speed lock up is requested to attain high C/N and low power consumption in the intermittent reception, etc. In the case of the normal frequency synthesizer device, the setting interval of the output frequency of the voltage-controlled oscillator is limited by the comparison frequency of the phase comparator. In order to obtain the finer setting interval, the comparison frequency must be lowered, so that the lock-up time cannot be shortened.
As the frequency synthesizer device that can shorten the lock-up time, there is the frequency synthesizer device that is normally called the fractional-N system. As shown in FIG.4, this frequency synthesizer device comprises a voltage-controlled oscillator (VCO) 1 for oscillating a signal having a frequency in response to an input voltage, a first frequency divider 2 for frequency-dividing the frequency of the output signal of the VCO, a second frequency divider 5 for frequency-dividing a frequency of the reference signal, a phase comparator 3 for comparing phase of an output signal (fdiv) of the first frequency divider 2 with phase of an output signal (fref) of the second frequency divider 5 to output phase difference, a low-pass filter (LPF) 4 for smoothing an output of the phase comparator 3, and a frequency-division ratio control circuit 6 for controlling a frequency-division ratio by using the fdiv as a clock such that the frequency-division ratio is changed in time and a value of its time average contains a value below the decimal point.
As set forth in Patent Application Publication (KOKAI) Hei 8-8741, the frequency synthesizer device of this fractional N system can produce equivalently an average frequency-division ratio by changing the frequency-division ratio set in the first frequency divider in time in synchronism with the signal fdiv. Therefore, there is no need that the frequency of fvco should be set to integral multiple of the frequency of fref, so that the frequency of fref can be set high irrespective of the desired frequency interval in fvco. As a result, the lock-up time can be reduced. In the integrated circuit in which such frequency synthesizer device in the prior art is integrated on the same semiconductor substrate, since the frequency division ratio control circuit must perform a complicated operation, its circuit scale is large and such integrated circuit consists of digital circuits such as CMOS, etc.
However, in the integrated circuit in which analogue circuits and digital circuits are integrated on the same semiconductor substrate, like the frequency synthesizer device in the prior art, since the maximum power is consumed at change points of the clock for the digital circuits, potential of the semiconductor substrate and potential of the power supply are varied in synchronism with the clock. Therefore, there are problems such that variation in these potential generates the noise, degrades the C/N of the frequency synthesizer device, and prevents the realization of high C/N and high-speed lock-up. Also, there is another problem such that, as the comparison frequency is set higher to put the feature of the fractional-N system to practical use, the noise generated by the frequency-division ratio control circuit is increased to increase the C/N degradation. In addition, there is still another problem such that, if both the transmitter portion and the receiver portion are integrated on the same semiconductor substrate even though the characteristics as the frequency synthesizer device can be satisfied, the transmitting/receiving characteristics are degraded because of the interference of the noise generated by the frequency-division ratio control circuit.
The present invention has been made to overcome such problems, and it is an object of the present invention to provide a frequency synthesizer device capable of reducing noises generated by a frequency-division ratio control circuit to improve a C/N ratio, reducing a lock-up time, and reducing a power consumption and a mobile radio device using the same.
In order to overcome the above subjects, in the present invention, a frequency synthesizer device is constructed by comprising a voltage-controlled oscillator for oscillating a signal having a frequency in response to an input voltage; a first frequency divider for frequency-dividing a frequency of an output signal of the voltage-controlled oscillator; a second frequency divider for frequency-dividing a frequency of a reference signal; a phase comparator for outputting a signal of phase difference between the first frequency divider and the second frequency divider to the voltage-controlled oscillator via a low-pass filter; and a frequency-division ratio control circuit for controlling the first frequency divider such that a frequency division ratio of the first frequency divider is changed in time and a time average value contains a value below the decimal point, whereby these circuits are integrated on a same semiconductor substrate; wherein a means for setting a power supply voltage supplied to the frequency-division ratio control circuit lower than a power supply voltage supplied to other circuits is provided.
According to such configuration, the variation in the substrate potential and the variation in the power supply voltage generated by the operation of the frequency-division ratio control circuit can be reduced by lowering the power supply voltage applied to the frequency-division ratio control circuit, so that the degradation of C/N can be reduced and also the power consumption can be reduced because of the lower voltage of the frequency-division ratio control circuit. This is because normally the power consumption of the CMOS circuit can be represented by Cxc3x97VDDxc3x97VDDxc3x97f (where C: parasitic capacitance, VDD: power supply voltage and signal voltage, and f: operating frequency) and thus the variation in the substrate potential and the variation in the power supply voltage depend on a change amount of the current flowing through the transistor.
Also, the frequency synthesizer device is constructed such that a power supply voltage is supplied to the frequency-division ratio control circuit from a power supply in other circuit via a resistor in an integrated circuit. According to such configuration, another power supply on the outside of the integrated circuit can be omitted, thus the number of parts can be reduced, also power supply voltage control can be simplified, and also the number of terminals of the integrated circuit can be reduced.
Also, the frequency synthesizer device is constructed such that a power supply voltage is supplied to the frequency-division ratio control circuit from a power supply in other circuit via a diode in the integrated circuit. According to such configuration, propagation of the noises from the frequency-division ratio control circuit to other power supply voltages can be reduced.
Also, a radio portion device is constructed in which a transmitter portion and a receiver portion as well as the frequency synthesizer device having the above configuration are integrated on a same semiconductor substrate. According to such configuration, degradation of the modulation/demodulation precision in the transmitter portion and the receiver portion can be reduced.
In addition, a mobile radio device is constructed by comprising the frequency synthesizer device or the radio portion device whose power supply voltage is lowered. According to such configuration, lower power consumption can be achieved and thus a speaking time and a standby time can be increased.